Unlike asynchronous DRAM, the synchronous DRAM, as the name suggests requires a clock. The synchronous DRAM offers burst mode and the internal buffers fills a bunch of data — then for each clock the data is shifted out like a shift register.
The burst mode is available in 1,2,4, 8 or full row in order to make access faster.
DATA OUT BUFFER).
Because the device now is synchronous. Then any operations and commands needs to be signaled first, then clocked.
From the table above, we can use the
LOAD MODE REGISTER command to push in Op-Code over the address bus.
Advanced features in SDRAM supports command pipelining — we can issue a new command before the previous command has completed. In the following diagram, note that the delay from start of command to getting the first bit of data is 5 clock cycles. So if we want to get more data after the four pieces of burst data as seen below, it would be slow if we start issuing new command after all the data has come out.
Hence, we can use the time where the chip is clocking out the data to pipeline new commands. Note that on the positive edge of clock cycle #5, we started issuing new read command — and the burst output is continuous.
Instead of just synchronizing on positive edge of the clock, but we transfer data on both positive and negative edge. Theoretically, we can get data from memory twice as fast. In reality, the performance is marginally better.