DRAM is voliltile storage memory. Generally they are randomly accessible.
💪 It’s major advantage over SRAM:
👍 The drawbacks of DRAW is:
In 8 or 16 bit microcontrollers, we don’t usually want to interface with DRAM. One reason is that there is not enough address space for the massive storage provided by DRAM.
The DRAM cell works by using a single transistor to charge/discharge a capacitor. The capacitor then stores the memory bit as the charge state.
Reading is more complicated because by reading, we destory the data so we have to somehow put that data bcak.
Present the row address, and latch it using RAS*
Present the column address and latch it using CAS*
An external multiplexer must be responsible to switch the two addresses to the DRAM
Data remains valid until negation of CAS* or RAS*
Data becomes available some delay later.
All DRAM has a feedback loop to “repair” the data after read operation. Upon read, the feedback circuit either fully charge or discharge the circuit.
The fact that we need to precharge to precisely VDD/2 slows down the reading cycle time. The result is that the DRAM cycle time is twice as long as the access time.
DRAM cells can be corrupted by cosmic particles, which causes random bit failures. First geneation of DRAM had problems with α-particles that penetrates and changes the state of the cells.
More critical systems that require the reliability feature ECC memory that exists to allow detection and correction of bit errors. It uses extra bits to calculate where the faulty cell is and restore it.
DRAM is leaky over time, and refreshing is necessary because if don’t access a part of memory frequently, the data gets corrupted. Refreshing is operated periodically.
The refresh counter and refresh contorl & timing circuit is used to manage this task.
We can read the data to refresh it too. This is common in graphic memories. Since for every frame, we need to draw to the screen and read data from the frame buffer periodically anyway, and thus a explicit refresh is not required.