Consider what happens when we have multiple clock domains (such as a case study in Lab 1, where there’s a fast clock and a slower clock). Crossing might occur.
Consider two flip flops driven by two clocks with different frequencies. Since the two frequencies are never in sync, the input to the second flip flop has no guarantee that it is the output from the first FF. Problem occurs when we sample input of the second FF when the first FF is still in its setup time, etc.
Flip flop specifications are violated.
The probability of occurrence of crossing for two clocks is given by
For async. signals such as interfacing with the outside, it is impossible to avoid this problem.
What happens when we violate FF’s setup time and hold time requirements?
At all times, the output
Q of the FF can either be the:
Note that metastable occurs because in reality, it takes time to transition between 0 and 1
A metastable signal may cause system-wide failure since the signal cannot be interpreted.
Consider the RS Latch, which is a part of the FF; we operate this under the condition that the outputs are always inversed of each other (property of RS latch).
If the set signal is high, output Qa goes to 1, if reset goes to high, output Qa goes to 0. We normally use it under the condition that we only press one of the at a time.
Now we add some gates and construct a gated RS latch. When the clock is high, it operates like a normal RS latch, if the clock input is low, the the latch remains its value regardless of RS. The gated RS latch is level sensitive.
Now we set the second input to
not D - this is a gated D latch, which is also level sensitive.
How does Metastability Happen?
Consider even number of inverters hooked up in a loop. If we give it a short pulse. Ideally, this would oscillate forever as the pulse loops back. In reality the pulse will either get narrower or wider until the pulse is gone.
Theoretically, in steady state, nothing changes. But in reality, there are noise which will knock the signals high and low at random, unpredictable times.
How can metastability cause failure?
If we have an async. data input into a register, whose output is fed into a combinational logic with delay. If the combinational delay is large enough (little slack time), we don’t get a stable signal. and metastability can occur and wrong value is sampled.
The mean time between failure is given by:
One solution is to run the clock much slower, this gives us more slack time. Obviously this is not very practical.
Another option is to eliminate possibility of metastability (only used asynchronous circuits - which is usually not feasible).
Finally, we can try handle metastability when it occurs. A metastability detector can be used that detects metastable circuits and emit a
In reality, designers give the signal more time to settle by giving it an extra cycle. (
page 45). The double-register design is used on each asynchronous input. If the signal between the two registers is metastable, it has an entire clock cycle to resolve.
Try double registers for each bit. But the problem is each one will take a different time for metastable signals to settle. An example would be an adder. The most significant bit in the adder (since it takes more logic) is slower than the other less significant bits. Thus, there is a chance that a wrong value is sampled.
To transmit, one option is gray-code which only allows one bit to be changed at a time.
Another option is to use a FIFO. The write side of the FIFO is clocked be the sender, and the reader side is clocked by the receiver. This works because the memory components itself is just a combinational circuit, and there is some FFs for
address that is clocked by the respective clock domains.
The FIFO also take cares of the flow control, something that would need to be implemented manually otherwise, which controls the read/write rate due to the difference clock speeds.