Often the speed of the circuit is constrained by:
The performance of an operation is given by the expression:
The number of cycles can be optimized by having a well designed datapath, the cycle time can be improved by increasing clock frequency (but only to a certain point).
Consider the simple logic of two inverters (
page 5). Recall from CPEN 211, that this is composed of a bunch of CMOS transistors. If the input is changing from HIGH to LOW, what is actually happening?
There are two cases for PMOS and NMOS transistors.
Nonetheless, there exists resistance. The resistance depends on the size of the transistor, the length of wire connecting the gates, and temperature.
Fact: There also exist parasitic capacitances attached to every wire and transistor due to physical transistor structure.
The capacitance depends on the size of transistor, the number of gates being driven (fan-out) and length of wire connecting the gates.
Fan-Out describes the number of gates connected down-stream.
Because of the parasitic capacitances, we get a RC model. Thus the delay comes from the transient behavior of the RC circuit.
The analysis tool creates an equivalent circuit of resistor and capacitor and solves for the time it takes to reach steady state. The tool takes in account of all variables such as transistor size, temperature and solves the equations.
The delay comes from:
The delay for both is modelled as one entity which helps with the simplicity of calculations.
The gate delay, denoted by , is the time that it takes for combinational gate to output change after the input changes.
The path delay, denoted by , is the delay through a series of combinational gates. Specifically, this is the time it takes for the output of the series of gates to change after the inputs to the path has changed.
The critical path delay is the delay in the longest in the path used.
Problem: the signals are all coming out at the different times, so we need to synchronize them.
If the is 5 ns, then we can’t have a clock frequency with period less than the delay time. For combinational logic, slower clock doesn’t matter as it will just give more time for the output to settle.
The FF has data input, output, and clock input. The input is stabilized at some point, then comes the clock. The clock then samples the input. But the output
q still will take some time to take effect.
The clock-to-Q delay, denoted as , it the delay between rising edge of clock, and when output changes.
Just like how the output needs some time to take effect, there also exists some delay for the input to take effect. Hence:
The setup time, denoted by , is the minimum time that the input to the flip-flop must be stable / settled right before the clock edge. The input should not change during this period.
Input value must be ready for destination flop ahead of when the rising clock edge arrives.
Now the critical path goes through:
Setup time violations can be fixed by:
The hold time, denoted by , is the minimum time required for the input to be stable right after the clock edge. The input should not change during this period.
If the input change before within hold time, then we cannot guarantee that the input is successfully sampled by the clock edge.
Input value of destination flop must hold after rising clock arrives.
Long hold times can cause problems with the faster non-critical paths. The fast path settles very quickly but the destination FF is still reading in “old” value from fast path logic.
Thus, the hold time needs to account for:
Hold time requirements can only be fixed by increasing the delay in the non-critical paths by adding buffers, which are pairs of inverters. This cannot be addressed by changing the clock frequency.