Last updated 2018-02-21 by Muchen

Problem Set 1

Q1

Q2

 
x
module Q2(
    input logic clk,
    input logic reset,
    output logic outs
);
    // Initialized values
    parameter y0_i = 1'b1;
    parameter y1_i = 1'b0;
    parameter y2_i = 1'b0;
    parameter y3_i = 1'b0;
    parameter y4_i = 1'b0;
    parameter y5_i = 1'b0;
    reg y0, y1, y2, y3, y4, y5;
    // Assuming active HIGH async reset
    always_ff @(posedge clk, posedge reset) begin
        if (reset) begin
            y0 <= y0_i;
            y1 <= y1_i;
            y2 <= y2_i;
            y3 <= y3_i;
            y4 <= y4_i;
            y5 <= y5_i;
        end else begin
            y0 <= y4 ^ y5;
            y1 <= y0;
            y2 <= y1;
            y3 <= y2;
            y4 <= y3;
            y5 <= y4;
        end
    end
    assign outs = y5;
endmodule

Q3

 
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// Accumulator
module Q3(
    input logic [15:0] data,
    input logic valid,
    input logic clk,
    input logic reset,
    output logic [15:0] sum
);
    reg [15:0] accum;
    // assuming active HIGH synchronous reset
    always_ff @(posedge clk) begin
        if (reset) begin
            accum <= 0;
        end else begin
            accum <= accum + (valid ? data : 0);
        end
    end
    assign sum = accum;
endmodule

Q4

 
x
module Q4(
    input logic stb,
    input logic clk,
    output logic ts,
    output logic tl
);
    logic start;
    logic [3:0] count1, count2;
    
    // STB is active low
    always_ff @(posedge clk, negedge stb) begin
        if (stb == 1'b0) begin
            start <= 1'b1;
        end else begin
            if (start == 1'b1) begin
                start <= 0;
                count1 <= 4;
                count2 <= 7;
            end else begin
                if (count1 != 0) count1 = count1 - 1'b1;
                if (count2 != 0) count2 = count2 - 1'b1;
            end
        end
    end
    assign ts = (count1 == 0);
    assign tl = (count2 == 0);
endmodule

Q5

 
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// Assuming 8-bit data
// IIR filter
// DF1
module Q5(
    input logic [7:0] xn,
    input logic [7:0] a1,
    input logic [7:0] a2,
    input logic [7:0] b1,
    input logic [7:0] b2,
    input logic clk,
    output logic [7:0] yn
);
    logic [7:0] dx1, dx2, dy1, dy2;
    always_ff @(posedge clk) begin
        dx1 <= xn;
        dx2 <= dx1;
        dy1 <= yn;
        dy2 <= dy1;
    end
    assign yn = (b1 * dx1) + (a1 * dy1) + ((b2 * dx2) + (a2 * dy2)) + xn;
endmodule